1. Field of the Invention
The present invention relates to solid-state imaging devices having a plurality of light receiving elements arranged two dimensionally in an imaging area, a vertical transfer register and a horizontal transfer register for transferring signal charges of the plurality of light receiving elements, and a shunt wire for sending clock pulses to a transfer electrode of the vertical transfer register, and more particularly, to solid-state imaging devices having a large imaging area.
2. Description of the Related Art
Interline-transfer solid-state imaging devices have been conventionally provided as various image sensors and for digital cameras.
FIG. 1 is an outlined view of a general interline-transfer solid-state imaging device. In the solid-state imaging device, light receiving elements 20 are disposed in an imaging area 10 almost in a two-dimensional matrix manner in a vertical direction (row) and a horizontal direction (column). These light receiving elements 20 convert light incident on a light receiving surface to signal charges having the amount of charges corresponding to the amount of the light, and accumulate them.
A vertical transfer register 30 is disposed at each vertical column of the light receiving elements 20, and a horizontal transfer register 40 is disposed next to the ends of the vertical transfer registers 30 in their transfer direction. An output section 50 is formed next to the end of the horizontal transfer register 40 in its transfer direction.
The solid-state imaging device has a dummy pixel area 60 having a structure similar to that of the light receiving elements 20 but not accumulating signal charges, close to the horizontal transfer register 40 in the imaging area 10. The dummy pixel area 60 is used, for example, for detecting a dark current to set a black level. The position of the dummy pixel area 60 is not limited to the position shown in FIG. 1. The dummy pixel area 60 can be formed at any position close to an end of a light receiving area.
In such solid-state imaging devices, especially in solid-state imaging devices used for video units having large screens, further especially in solid-state imaging devices used for HDTV, for which a high output rate is required, since it is necessary to drive vertical transfer registers at a high speed, shunt wires are generally provided as means for sending a clock signal to the vertical transfer registers.
FIG. 2 is a plan showing an outlined structure of a conventional solid-state imaging device having shunt wires. FIG. 3 is a partial enlarged plan showing a wire structure in an imaging area of the solid-state imaging device shown in FIG. 2.
As shown in FIG. 2, in the solid-state imaging device, light receiving elements (not shown) and vertical transfer registers (not shown) are provided inside an imaging area 10, and a horizontal transfer register 21 and an output section 22 are provided outside the imaging area 10.
Shunt wires 30 are provided in a vertical direction along the vertical transfer registers in an upper layer of the imaging area 10.
Signal lines 31, 32, 33, and 34 of the shunt wires 30 are connected to bus wires 40 disposed in an area outside the imaging area 10 and opposite the horizontal transfer register 21.
Signal lines (bus lines) 41, 42, 43, and 44 of the bus wires 40 are formed in concentric closed-loop manners, and independently connected to electrode pads 51, 52, 53, and 54 to be connected to external wires of the imaging device chip, respectively, with parts of the closed loops being externally extended.
As shown in FIG. 3, the signal lines 31, 32, 33, and 34 of the shunt wires 30 are connected to transfer electrodes (poly-Si electrodes) 64, 63, 62, and 61 of the vertical transfer registers, respectively, through contact sections 35.
In the present case, four-phase clock driving is performed. The signal lines 31, 32, 33, and 34 of the shunt wires 30, the signal lines 41, 42, 43, and 44 of the bus wires 40, the electrode pads 51, 52, 53, and 54, and the transfer electrodes 64, 63, 62, and 61 correspond to each other, respectively, and four sets of four types of components are provided.
In the conventional wire structures such as that described above, however, if the solid-state imaging device has a large chip size, or the frequency of its clock signal is too high, since a propagation delay occurs in the shunt wires 30, the clock signal does not have a satisfactory waveform at the end opposite the end where the bus wires 40 are located, its effective amplitude becomes low, and the amount of charges handled by the vertical transfer registers is reduced.
In a large-sized solid-state imaging devices, since the above problems become more prominent, high-speed driving becomes impossible and a larger number of pixels are unlikely to be provided. The number of frames per unit period cannot be increased, and larger-sized solid-state imaging devices are unlikely to be provided.